The present invention relates generally to memory devices, and in particular, to a method of outputting data from a memory device.
As semiconductor manufacturing techniques and processes continue to improve, the size of elements on a integrated circuit continues to decrease, and therefore the number of elements on an integrated circuit continues to increase. One area of semiconductor technology where such improvements can be seen is the manufacture of memory devices, such as dynamic random access memories (DRAMs). While increases in the density of integrated circuits provide many advantages, such increases often result in incompatibility with other devices.
One such example of an increase in density creating compatibility issues has been seen in the transition from DRAMs having a memory size of 64M cells to DRAMs having 256M cells. During this transition, a DRAM having an intermediate memory size of 128M was introduced, in part because of the inability of many memory manufacturers to transition to a memory size of 256M in one step with a cost effective process and die size. In addition to simpler manufacturing, the 128M memory also has the advantage that the number of row addresses is the same as for 64M memory, and the 128M memory could be handled by controllers built for the 64M DRAMs. Some users of DRAMs, such as computer server customers with large memory demands, use stacked devices to maximize available memory on a DIMM. However, as the sizes of the memory grows, older memory controllers will again not be able to handle one chip with an additional row address. A large DRAM which comes early into the market has a limited number of applications since most memory controllers are not designed to support the new size as a single device, especially when a new address is added.
Accordingly, there is a need for memory device and method of an internal DRAM architecture by which a DRAM can be operated like a stacked device with two chip select signals or like a single large device with an additional row address.
This invention describes an internal architecture by which a memory device such as a DRAM can be operated like a stacked device with two CS signals or like a single large device with an additional row address. By giving the integrated circuit the ability to be operated like a stacked (pin-out according to the dual-chip package spec) component or like one device of the next generation chip, one die can be used to cover a larger part of the market and make the transition to a next generation easier.